`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:57:20 10/21/2010 
// Design Name: 
// Module Name:    host_interface 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module host_interface(
 		input	wire [7:0]	hi_in,
		output	wire [1:0]	hi_out,
		inout	wire [15:0]	hi_inout,
		output	wire		i2c_sda,
		output	wire		i2c_scl,
		output	wire		hi_muxsel, 
		output  wire		ti_clk,
		output	wire [15:0]	pipe_out,
		output  wire 		pipe_has_data,
		output  wire [15:0] wire_out,
		output 	wire [15:0] trigger_out
		);

	
//Declerations
	wire [30:0]		ok1; 			// data from HostInterface
	wire [16:0]		ok2; 			// data to HostInterface

//Assignments
	assign i2c_sda = 1'bz;
	assign i2c_scl = 1'bz;
	assign hi_muxsel = 1'b0;
//HostInstantitaion
	 
	okHost okHI (   .hi_in( hi_in ),
					.hi_out( hi_out ),
					.hi_inout( hi_inout ),
					.ti_clk( ti_clk ),
					.ok1( ok1 ),
					.ok2( ok2 ) 
	);	


//Wire In
	
	//EP 0
	okWireIn wireIn (.ok1(ok1), .ep_addr( 8'h00 ), .ep_dataout( wire_out[15:0]));

//Pipe In	

	//EP 156
	okPipeIn pipeIn (.ok1(ok1), .ok2(ok2),.ep_addr( 8'h9c), .ep_dataout(pipe_out[15:0]), .ep_write(pipe_has_data));

//Trigger In
	
	//EP 83
	okTriggerIn triggerIn (.ok1(ok1), .ep_clk(ti_clk), .ep_addr(8'h53), .ep_trigger(trigger_out[15:0]) );

endmodule
